The present invention relates to a nonvolatile semiconductor memory device including a floating gate electrode and a method for fabricating the same, and more particularly relates to measures taken for improving drain-disturb characteristics.
Conventionally, a nonvolatile semiconductor memory device having a memory cell structure, in which a memory cell transistor including a floating gate electrode is formed, has been known as a means for realizing even higher degree of integration. Such nonvolatile semiconductor memory devices are disclosed, for example, in Japanese Laid-Open Publication No. 60-134477 and an article entitled "Process and Device Technologies for 16 Mbit EPROMs with Large-Tilt-Angle Implanted P-Pocket Cell", IEDEM 90, pp. 95-98.
FIG. 16(a) is a cross-sectional view illustrating a memory cell structure of the nonvolatile semiconductor memory device described in the above-identified article. As shown in FIG. 16(a), a stacked gate portion 110 is formed on a p-type Si substrate 101 in each memory cell. The stacked gate portion 110 includes: a gate oxide film 102 functioning as a tunnel insulating film, too; a floating gate electrode 103 made of polysilicon; a capacitive insulating film 104 made of ONO; and a control gate electrode 105 made of polysilicon. A protective insulating film 106 is provided over the stacked gate portion 110. In the p-type Si substrate 101, an n.sup.++ drain layer 126a (n.sup.++ deep drain) and an n.sup.++ source layer 126b, each layer containing arsenic (As) at a high concentration; an n.sup.+ drain layer 123 (shallow drain) containing arsenic at a low concentration; and a pair of p-pockets 124a, 124b, containing phosphorus (P) and functioning as punch through stoppers, are formed.
FIG. 16(b) is a flow chart illustrating the process steps for fabricating this nonvolatile semiconductor memory device. First, after the stacked gate portion 110 has been defined, arsenic ions are implanted to form the shallow drain (n.sup.+ drain layer 123). Next, boron (B) ions are implanted in accordance with large-angle-tilt ion implantation technique, thereby forming the p-pockets 124a, 124b. Then, after peripheral transistors have been formed, arsenic ions are implanted again to form the deep drain (n.sup.++ drain layer 126a) and a heat treatment is conducted, thereby activating the impurities implanted into the respective regions. Thereafter, n-type impurity ions are implanted at a low concentration to form LDD regions for the peripheral transistors. Though not illustrated in FIG. 1 of that article, insulator sidewalls seem to be formed on the side surfaces of the stacked gate portion 110 as indicated by the broken lines in FIG. 16(a). And the ion implantation for forming the deep drain seems to be performed using the stacked gate portion 110 and the insulator sidewalls as a mask.
Next, the operation of the conventional nonvolatile semiconductor memory device will be described.
A write operation is performed by applying a voltage of about 10 V to the control gate electrode 105 and a voltage of about 5 V to the n.sup.++ drain layer 126a, generating channel hot electrons in the vicinity of the junction between the p-pocket 124a and the n.sup.+ layer 123 and injecting and accumulating the channel hot electrons in the floating gate electrode 103. An erasure operation is performed by applying a voltage of about 12 V to the n.sup.++ source layer 126b and making FN (Fowler-Nordheim) tunneling current take out the electrons accumulated in the floating gate electrode 103. And a read operation is performed by applying a voltage of about 5 V to the control gate electrode 105 and a voltage of about 1 V to the n.sup.++ drain layer 126a and sensing the amount of electrons accumulated in the floating gate electrode 103 based on the level of drain current. If a sufficiently large number of electrons are accumulated in the floating gate electrode 103, then drain current hardly flows. On the other hand, if substantially no electrons are accumulated in the floating gate electrode 103, then drain current flows abundantly. In accordance with the difference in levels of the drain current, the stored information can be read out.
It is known that in such a nonvolatile semiconductor memory device, the more abrupt the p-n junction between the p-pocket 124a and the n.sup.+ drain layer 123 is, the larger number of hot electrons are generated during writing. Since the p-pockets 124a, 124b ensure the prevention of punch-through phenomenon, a very fine-line memory cell structure with a gate length as small as about 0.4 .mu.m is allegedly realized.
However, the nonvolatile semiconductor memory device having a memory cell structure including a shallow drain as disclosed in the above-identified article has the following problems.
In performing a write operation on a memory cell, voltages of about 5 V and about 0 V are respectively applied to the drain and the control gate electrode of a non-selected memory cell connected to a selected bit line, to which a selected memory cell is connected in common. In this case, if electrons have been injected into a floating gate electrode, the potential in the floating gate electrode is about -2 V. As a result, a considerably high electric field is generated between the floating gate electrode and the drain. And in the vicinity of the drain, so-called "gate induced drain leakage current (GIDL)", or a large number of electron-hole pairs, is generated. Then, the holes are attracted to the electric field to enter the gate oxide film (i.e., hot hole traps are generated) or reach the vicinity of the floating gate electrode. The accumulation of holes in the gate oxide film causes the following two disadvantages.
Firstly, since the number of electrons accumulated in the floating gate electrode decreases, the threshold voltage of a non-selected memory cell transistor adversely varies during writing (drain-disturb phenomenon). As a result, erroneous writing possibly happens.
Such variation in threshold voltages is more likely to occur if a high voltage has been continuously applied between the floating gate electrode and the drain of the memory cell for a long time. In this case, as the degree of integration of a nonvolatile semiconductor memory device is higher, the number of memory cells connected to a single bit line increases correspondingly. For example, in an array of 1-Mbit memory cells, 1,024 memory cells are connected to a common bit line. Thus, in performing a write operation on such a memory, a high voltage is continuously applied between the floating gate electrode and the drain of a single memory cell for as long as 1 second or more. This time interval will tend to get longer as an even higher degree of integration is realized for a nonvolatile semiconductor memory device. In other words, in order to further increase the degree of integration for a nonvolatile semiconductor memory device, it is indispensable to improve the drain-disturb characteristics.
Secondly, since the accumulation of holes deteriorates the quality of a gate oxide film, the reliability is adversely deteriorated.